个人简历：
教育背景
2004~2008 南开大学 微电子学与固体电子学 学士
2008~2011 北京大学 微电子学与固体电子学 硕士
2014~2020 中国科学院大学 微电子学与固体电子学 博士
工作简历
2011~2018 中国科学院微电子所研究实习研究员、助理研究员
2014~2018 武汉新芯、长江存储资深工程师
2019~2023 中国科学院微电子所副研究员
2023~至今 南开大学电光学院副教授
科研项目
l 负责国家自然科学基金重大研究计划面向集成电路光刻工艺的功能团簇材料研究子课题
l 负责华为、蚂蚁企业计算机硬件安全方向横向项目
l 主持企业原子层沉积设备开发及工艺验证横向课题
l 主持南开大学-青年教师研究项目-三维铪基铁电存储器应力效应研究
l 负责国家重点研发项目高灵敏度脑电信号采集处理和无线传输技术研究子课题
l 主持中国科学院青促会项目三维存储器中高密度低成本的字线台阶结构设计及工艺研究
l 参与国家存储器基地建设先进三维NAND型闪存存储器芯片集成工艺研究及其产业化
l 参与国家极大规模集成电路制造装备及成套工艺子课题：体硅FinFET与关键工艺研究
l 参与国家极大规模集成电路制造装备及成套工艺子课题：22纳米工艺整合及集成技术
论文/专利/教材
代表性论文：
[1]Zhixin Ren,Peizhen Hong*, et al. FRAM PUF Schemes under MEC: Architecture and Performance Evaluation.IEEE 8th International Conference on Electronic Information and Communication Technology (ICEICT). IEEE, 2025: 570-573.
[2]Jing Zhou, Yue Guan, Peizhen Hong, Shuai Ning, & Feng Luo, Improving the endurance for ferroelectric Hf0. 5Zr0. 5O2 thin films by interface and defect engineering. Applied Physics Letters, 2024,124(9).
[3]Runhao Han, Peizhen Hong*， Zhang B, et al. Understanding the stress effect of TiN top electrode on ferroelectricity in Hf0. 5Zr0. 5O2 thin films[J]. Journal of Applied Physics, 2023, 134(19).
[4]Mingkai Bai, Peizhen Hong*,Runhao Han,et al. Regulating ferroelectricity in Hf0. 5Zr0. 5O2 thin films: Exploring the combined impact of oxygen vacancy and electrode stresses[J]. Journal of Applied Physics, 2023, 134(17).
[5]Runhao Han, Peizhen Hong*，Shuai Ning, et al. The effect of stress on HfO2-based ferroelectric thin films: A review of recent advances[J]. Journal of Applied Physics, 2023, 133, 240702 (Editor`s Pick)
[6]Runhao Han, Peizhen Hong*, Jingwen Hou, Bao Zhang, et al, The Top Electrode Tensile Stress Effect on Ferroelectricity of Hf0.5Zr0.5O2 Thin Films,2023 7th IEEE Electron Devices Technology & Manufacturing Conference (IEEE EDTM 2023), Seoul Korea,2023.3（Invited Report）
[7]Bao Zhang, Peizhen Hong, Jingwen Hou, et al. Doped HfO2-based ferroelectric-aided charge-trapping effect in MFIS gate stack of FeFET[J]. Journal of Applied Physics, 2023, 133(16)
[8]Peizhen Hong, Qiang Xu, Jingwen Hou, Mingkai Bai, Zhiguo Zhao, et al. Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions[J].Semiconductor Science and Technology, 2021, 37(2): 025007
[9]Bao Zhang, Siwei Mao，Chunlong Li，Peizhen Hong，Jingwen Hou，et al.Dual-axis control of magnetic anisotropy in single crystal Co2MnSi thin film through piezo-voltage-induced strain[J]. Nanoscale advances, 2022, 4(16): 3323-3329
[10]Bao Zhang, Chunlong Li, Peizhen Hong, Zongliang Huo. Ferroelectric control of the perpendicular magnetic anisotropy in PtCoRu/Hf0.5Zr0.5O2 heterostructure[J].Applied Physics Letters, 2021, 119(2): 022405-1-6
[11]Peizhen Hong, Zhiguo Zhao, Jun Luo, Zhiliang Xia, Xiaojing Su, Libin Zhang, Chunlong Li, Zongliang Huo.An Improved Dimensional Measurement Method of Staircase Patterns with Higher Precision in 3D NAND[J]. IEEE Access, 2020, 8: 140054-140061.
[12]Peizhen Hong, Zhiliang Xia, Huaxiang Yin, Chunlong Li and Zongliang Huo.A High Density and Low Cost Staircase Scheme for 3D NAND Flash Memory: SDS(Stair Divided Scheme)[J].ECS Journal of Solid State Science and Technology, 2019, 8(10): P567.
[13]Lingkuan Meng, Peizhen Hong, Xiaobin He, et al. Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devices[J]. Applied Surface Science, 2016, 362:483-489.
[14]Changliang Qin, Guilei Wang, Peizhen Hong, et al, Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22nm all-last high-k/metal-gate pMOSFETs[J]. Solid State Electronics, 2016, 123:38-43.
[15]Xiaolong Ma, Huaxiang Yin, Peizhen Hong, et al, Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-VTH Operation on Si Substrate[J]. ECS Solid State Letters, 2015, 4(4).
[16]Xiaolong Ma, Huaxiang Yin, Peizhen Hong, et al, Gate-All-Around Silicon Nanowire Transistors with channel-last process on bulk Si substrate[J]. IEICE Electronics Express, 2015, 12(7): 20150094-20150094.
[17]Peizhen Hong, Zhiguo Zhao, Chunlong Li, Lingkuan Meng, Yongkui Zhang, Xiaobin He,et al. Finfet gate etch towards 16nm CMOS technolodgy. Proc.of the 225th Electrochemical Society(ECS) Meeting, Orlando, American, 2014.
[18]Qingzhu Zhang, Peizhen Hong, Hushan Cui, et al, A Novel Self-Aligned Source/Drain Contact Technology, Micronanoelectronic Technology, 2014.
[19]Peizhen Hong, Zhongyang Guo, Zhenchuan Yang, Guizhen Yan. A method to reduce notching effect on the anchors of a microgyroscope. Proc. of the 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems(MEMS) , Kaohsiung, Taiwan,2011：346-349.
[20]Liang Qian, Peizhen Hong, Lina Sun, Guizhen Yan, CMOS compatible Process for Suspended High-Aspect-Ratio Integrated Silicon Microstructures. Proc. of the 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems(MEMS) , Kaohsiung, Taiwan,2011：405-408.
授权中国专利
[1] 半导体器件及其制造方法，ZL201210246436.X 发明人：秦长亮，洪培真，殷华湘
[2] 半导体器件制造方法，ZL201210246706.7 发明人：秦长亮，洪培真，殷华湘
[3] 半导体器件制造方法，ZL201210495187.8 发明人：秦长亮，尹海洲，洪培真，殷华湘，王桂磊，赵超
[4] 半导体器件制造方法，ZL201210497474.2 发明人：秦长亮，尹海洲，洪培真，殷华湘，王桂磊，赵超
[5] 半导体器件制造方法，ZL201310269697.8 发明人：秦长亮，尹海洲，洪培真，殷华湘，徐强，李俊峰，赵超
[6] 一种自对准接触孔刻蚀工艺方法，ZL201310438771.4 发明人：李俊杰，李春龙，李俊峰，王文武，洪培真
[7] 一种纳米线及阵列的形成方法，ZL201310542253.7 发明人：洪培真，马小龙，殷华湘，徐秋霞，李俊峰，赵超
[8] FinFET及其制造方法，ZL201310119849.6 发明人；朱慧珑，洪培真，殷华湘
[9] 半导体器件及其制造方法，ZL201310141764.8 发明人：殷华湘，洪培真，孟令款，朱慧珑
[10] 半导体器件制造方法，ZL201310173339.7 发明人：秦长亮，尹海洲，洪培真，殷华湘，李俊峰，赵超
[11] 堆叠纳米线制造方法，ZL201310110074.6 发明人：秦长亮，殷华湘，洪培真，马小龙，赵超
[12] 形成纳米线阵列的方法，ZL201410766450.1 发明人：洪培真，徐秋霞，殷华湘，李俊峰，赵超
[13] 一种硅深孔刻蚀方法，ZL201410571338.2 发明人：李俊杰，孟令款，李春龙，洪培真，崔虎山，李俊峰，赵超
[14] 鳍式场效应晶体管及其假栅的制造方法，ZL201410392773.9 发明人：洪培真，殷华湘，朱慧珑，刘青，李俊峰，赵超，尹海州
[15] 形成纳米线阵列的方法，ZL201410766448.4 发明人：洪培真，徐秋霞，殷华湘，李俊峰，赵超
[16] 形成级联纳米线的方法，ZL201410766446.5 发明人：洪培真，殷华湘，徐唯佳，马小龙，徐秋霞，李俊峰，赵超
[17] 形成纳米线阵列的方法，ZL201410768407.9 发明人：洪培真，徐秋霞，殷华湘，李俊峰，赵超
[18] 形成纳米线阵列的方法，ZL201410766482.1 发明人：洪培真，徐秋霞，殷华湘，李俊峰，赵超
[19] 一种形成栅极沟道的方法及对应的半导体，ZL201610473868.2 发明人：隋翔宇，唐兆云，高晶，霍宗亮，陆智勇，许刚，洪培真，龚睿，刘藩东，何佳
[20] 图形测试结构及其制作方法、测量图形尺寸的方法，ZL201611207746.5 发明人：洪培真，唐兆云，霍宗亮
[21] 存储器件的形成方法，ZL201710131749.3 发明人：华文宇，夏志良，蒋阳波，刘藩东，洪培真，傅丰华，杨要华，曾明，霍宗亮
[22] 一种三维存储器堆栈结构及其堆叠方法及三维存储器，ZL201710132047.7 发明人：洪培真，唐兆云，张高升，苏恒，隋翔宇，何佳，石晓静，骆中伟，华文宇，刘藩东
[23] 三维存储器及其形成方法，ZL201710132422.8 发明人：徐强，刘藩东，霍宗亮，夏志良，杨要华，洪培真，华文宇，何佳
[24] 半导体结构及其形成方法，ZL201710134033.9 发明人：何佳，黄海辉，刘藩东，杨要华，洪培真，夏志良，霍宗亮，冯耀斌，陈保友，曹清晨
[25] 一种三维存储器件的制造方法及其器件结构，ZL201710726099.7 发明人：骆中伟，夏志良，华文宇，洪培真，张富山，李思哲，王迪，霍宗亮
[26] 一种顶层选择栅切线的刻蚀工艺方法，ZL201710733247.8 发明人：何佳，洪培真，华文宇，刘藩东，杨要华，夏志良，霍宗亮
[27] 一种标记图形及其形成方法，ZL201710740889.0 发明人：李思哲，华文宇，洪培真，夏志良，骆中伟，霍宗亮
[28] 一种形成多层复合膜的方法及三维存储器件，ZL201710755059.5 发明人：王迪，华文宇，夏志良，骆中伟，张富山，洪培真，李思哲
[29] 一种用于3D NAND的核心区层间绝缘氧化层CMP方法，ZL201710761488.3 发明人：洪培真，杨俊铖，周小红，夏志良，万先进，霍宗亮
[30] 3D存储器的蚀刻方法，ZL201710761489.8 发明人：洪培真，刘藩东，华文宇，夏志良，霍宗亮
[31] 3D NAND存储器件台阶结构及其制造方法，ZL201710792181 .X 发明人：华文宇，夏志良，洪培真，骆中伟，李思哲，王迪
[32] 一种三维存储器件的制造方法及其器件结构，ZL201710774720.7 发明人：华文宇，李思哲，洪培真，骆中伟，夏志良，霍宗亮
[33] 存储结构及其制作方法，ZL201810209625.7 发明人：何佳，霍宗亮，夏志良，隋翔宇，陆智勇，龚睿，洪培真，刘藩东，吴娴
[34] 纳米线阵列围栅MOSFET结构及其制作方法，ZL201810143686.8 发明人：徐秋霞，周娜，李俊峰，洪培真，许高博，孟令款，贺晓斌，陈大鹏，叶甜春
[35] 三维存储器器件的复合衬底，ZL201880005190.2 发明人：华文宇，夏志良，蒋阳波，刘藩东，洪培真，傅丰华，杨要华，曾明，霍宗亮
[36] 字线结构与三维存储器件，ZL201880005524.6 发明人：徐强，刘藩东，霍宗亮，夏志良，杨要华，洪培真，华文宇，何佳
[37] 三维存储器设备的开口布局，ZL201880005594.1 发明人：何佳，黄海辉，刘藩东，杨要华，洪培真，夏志良，霍宗亮，冯耀斌，陈保友，曹清晨
[38] 一种三维铁电存储器及其制造方法，ZL201910227937.5 发明人：霍宗亮，李春龙，邹兴奇，洪培真，张瑜，靳磊
[39] 一种三维NAND型铁电存储器、制作方法及操作方法，ZL201910350185.1 发明人：霍宗亮，李春龙，张瑜，洪培真，邹兴奇，靳磊
[40] 一种三维NAND型铁电存储器、制作方法及操作方法，ZL201910349696.1 发明人：霍宗亮，李春龙，张瑜，洪培真，邹兴奇，靳磊
[41] 一种三维存储器及其制作方法，ZL201911202324.2 发明人：洪培真，李春龙，霍宗亮，邹兴奇，张瑜
[42] 三维存储器设备的开口布局，ZL202010840359.5 发明人：何佳，黄海辉，刘藩东，杨要华，洪培真，夏志良，霍宗亮，冯耀斌，陈保友，曹清晨
[43] 三维存储器器件的复合衬底，ZL202010587572.X 发明人：华文宇，夏志良，蒋阳波，刘藩东，洪培真，傅丰华，杨要华，曾明，霍宗亮
[44] 一种三维NAND存储器及其制造方法，ZL202010185973.2 发明人：张保，李春龙，洪培真，霍宗亮
授权美国专利
[1] METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE,US9006057B2 Inventor：Changliang Qin,Peizhen Hong,Huaxiang Yin
[2] WORD LINE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE,US10651192B2 Inventor：Qiang Xu,Fandong Liu,Zongliang Huo,Zhiliang Xia,Peizhen Hong,Wenyu Hua,Jia He
[3] OPENINGS LAYOUT OF THREE-DIMENSIONAL MEMORY DEVICE,US10804283B2 Inventor：Jia He,Haihui Huang,Fandong Liu,Yaohua Yang,Peizhen Hong,Zhiliang Xia,Zongliang Huo,Yaobin Feng,Baoyou Chen,Qingchen Cao
[4] WORD LINE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE,US11222903B2 Inventor：Qiang Xu,Fandong Liu,Zongliang Huo,Zhiliang Xia,Yaohua Yang,Peizhen Hong,Wenyu Hua, Jia He
[5] OPENINGS LAYOUT OF THREE-DIMENSIONAL MEMORY DEVICE,US11574919B2 Inventor：Qiang Xu,Fandong Liu,Zongliang Huo,Zhiliang Xia,Yaohua Yang,Peizhen Hong, Yaobin Feng,Qingchen Cao,Baoyou Chen
[6] WORD LINE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE,US11792989B2 Inventor：Qiang Xu,Fandong Liu,Zongliang Huo,Zhiliang Xia,Yaohua Yang,Peizhen Hong,Wenyu Hua, Jia He
[7] OPENINGS LAYOUT OF THREE-DIMENSIONAL MEMORY DEVICE,US11903195B2 Inventor：Jia He,Fandong Liu,Zongliang Huo,Zhiliang Xia,Yaohua Yang,Peizhen Hong, Yaobin Feng,Qingchen Cao,Baoyou Chen
[8] METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE,US20140057404A1 Inventor：Changliang Qin,Peizhen Hong,Huaxiang Yin
[9] COMPOSITE SUBSTRATE OF THREE-DIMENSIONAL MEMORY DEVICES,US20190013326A1 Inventor：Wenyu Hua,ZHiliang Xia,Yangbo Jiang,Fandong Liu,Peizhen Hong,Fenghua Fu,Yaohua Yang,Ming Zeng,Zongliang Huo
[10] OPENINGS LAYOUT OF THREE-DIMENSIONAL MEMORY DEVICE,US20190013327A1 Inventor：Jia He,Haihui Huang,Fandong Liu,yaohua Yang,Peizhen Hong,Zhiliang Xia,Zongliang Huo,Yaobin Feng,Baoyou Chen,Qingchen Cao
[11] WORD LINE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE,US20190043883A1 Inventor：Qiang Xu,Fandong Liu,Zongliang Huo,Zhiliang Xia,Yaohua Yang,Peizhen Hong,Wenyu Hua, Jia He
[12] WORD LINE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE,US20200243557A1 Inventor：Qiang Xu,Fandong Liu,Zongliang Huo,Zhiliang Xia,Yaohua Yang,Peizhen Hong,Wenyu Hua, Jia He
[13] OPENINGS LAYOUT OF THREE-DIMENSIONAL MEMORY DEVICE,US20210151458A1 Inventor：Jia He,Haihui Huang,Fandong Liu,Yaohua Yang,Peizhen Hong,Zhiliang Xia,Zongliang Huo,Yaobin Feng,Baoyou Chen,Qingchen Cao
[14] WORD LINE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE,US20220059564A1 Inventor：Qiang Xu,Fandong Liu,Zongliang Huo,Zhiliang Xia,Yaohua Yang,Peizhen Hong,Wenyu Hua, Jia He
[15] OPENINGS LAYOUT OF THREE-DIMENSIONAL MEMORY DEVICE,US20230157020A1 Inventor：Jia He,Haihui Huang,Fandong Liu,Yaohua Yang,Peizhen Hong,Zhiliang Xia,Zongliang Huo,Yaobin Feng,Baoyou Chen,Qingchen Cao
[16] WORD LINE STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE,US20230413560A1 Inventor：Qiang Xu,Fandong Liu,Zongliang Huo,Zhiliang Xia,Yaohua Yang,Peizhen Hong,Wenyu Hua, Jia He
[17] OPENINGS LAYOUT OF THREE-DIMENSIONAL MEMORY DEVICE,US20240107757A1 Inventor：Jia He,Haihui Huang,Fandong Liu,Yaohua Yang,Peizhen Hong,Zhiliang Xia,Zongliang Huo,Yaobin Feng,Baoyou Chen,Qingchen Cao
教材
《存储器工艺与器件技术》霍宗亮，夏志良，靳磊，王颀，洪培真 编著,2023.8
授课
研究生专业必修课《高等半导体器件物理》《信息前沿技术》
本科生专业必修课《半导体器件物理》《创新研究与训练》《新生研讨课》
社会兼职
中国电子元器件关键材料与技术专委会委员,Journal of Advanced Dielectrics 期刊青年编委
